1. Field of the Invention
The present invention relates to an oscillation stop detection circuit which is suitable for use in a semiconductor integrated circuit (hereinafter called xe2x80x9cICxe2x80x9d) or the like having a oscillation circuit and detects the stop of oscillation thereof.
2. Description of the Related Art
As an IC such as a real-time clock or the like for creating a waveform having a predetermined cycle through the use of a crystal oscillator or a CR oscillator, using it for an internal synchronization or synchronous signal and outputting it to the outside, there is known one having a configuration wherein even during a period in which a power supply for a system is at a halt, backup power is supplied so that only an oscillation circuit or oscillator and its peripheral circuits continue to operate. When a backup state continues for a long time in the IC provided with such a backup function, a supply voltage such as a backup battery or the like is reduced after a while so that an oscillating operation is stopped. When the power supply for the system is turned on to bring the IC to its normal state after the stop of the oscillating operation, the oscillating operation is resumed but the time of a clock or the time of a timer results in a false value. However, it is not possible to recognize, through the use of the oscillator alone, whether the value is incorrect. Thus, the provision of an oscillation stop detection circuit for detecting the stop of an oscillating operation in a backup state inside an IC therefor becomes effective.
FIG. 6 is a circuit diagram of a conventional oscillation stop detection circuit.
The present oscillation stop detection circuit has an input terminal 11 supplied with a clock signal CLK from an unillustrated oscillator circuit. The gates of an N channel MOS transistor (hereinafter called xe2x80x9cNMOSxe2x80x9d) 12 and a P channel MOS transistor (hereinafter called xe2x80x9cPMOSxe2x80x9d) 13 are electrically connected to the input terminal 11. The source of the NMOS 12 is electrically connected to a ground potential GND, and the drain thereof is electrically connected to a node N1. The source of the PMOS 13 is electrically connected to a source potential VDD through a resistor 14, and the drain thereof is electrically connected to the node N11. Further, the input of an inverter 15 is electrically connected to the input terminal 11, and the gates of an NMOS 16 and a PMOS 17 are electrically connected to the output of the inverter 15. The source of the NMOS 16 is electrically connected to the ground potential GND, and the drain thereof is electrically connected to a node N12. The source of the PMOS 17 is electrically connected to the source of the PMOS 13, and the drain thereof is electrically connected to the node N12.
Capacitors 18 and 19 are respectively electrically connected between the nodes N11 and N12 and the ground potential GND. Further, the nodes N11 and N12 are respectively electrically connected to the input of a two-input OR gate (hereinafter called xe2x80x9cORxe2x80x9d) 20. The output of the OR 20 is electrically connected to an output terminal 21. When the clock signal CLK supplied to the input terminal 11 stops, a detection signal OUT is outputted from the output terminal 21.
FIG. 7 is a timing chart showing the operation of the oscillation stop detection circuit shown in FIG. 6.
When a clock signal CLK having a level xe2x80x9cHxe2x80x9d is inputted to the input terminal 11 at a time T1 in FIG. 7, the gates of the NMOS 12 and PMOS 13 go xe2x80x9cHxe2x80x9d. Thus, the NMOS 12 is brought to an on state and the PMOS 13 is brought to an off state, so that the node N11 is reduced to a level xe2x80x9cLxe2x80x9d.
On the other hand, the clock signal CLK is inverted by an inverter 15 from which it is supplied to the gates of the NMOS 16 and PMOS 17. Thus, the NMOS 16 is brought to an off state and the PMOS 17 is brought to an on state, so that the potential at the node N12 rises. However, since the source of the PMOS 17 is electrically connected to the source potential VDD through the resistor 14, and the capacitor 19 is electrically connected between the node N12 and the ground potential GND, the potential at the node N12 rises gently. Therefore, the potential at the node N12 reaches a threshold voltage Vt or less of the OR 20 for a while from the time T1, and a detection signal OUT outputted from the OR 20 goes xe2x80x9cLxe2x80x9d.
When the clock signal CLK inputted to the input terminal 11 changes to the level xe2x80x9cLxe2x80x9d at a time T2 while the detection signal OUT of the OR20 is xe2x80x9cLxe2x80x9d, the gates of the NMOS 16 and PMOS 17 go xe2x80x9cHxe2x80x9d. Thus, the NMOS 16 is brought to an on state and the PMOS 17 is brought to an off state, so that an electrical charge stored or charged in the capacitor 19 is discharged through the NMOS 16, and hence the node N12 is reduced to the level xe2x80x9cLxe2x80x9d.
On the other hand, the NMOS 12 is brought to an off state and the PMOS 13 is brought to an on state, so that the potential at the node N11 rises. Since, however, the source of the PMOS 13 is electrically connected to the source potential VDD through the resistor 14 and the capacitor 18 is electrically connected between the node N11 and the ground potential GND, the potential at the node N11 rises gradually. Therefore, the potential at the node N11 reaches the threshold voltage Vt or less of the OR 20 for a while from the time T2, and a detection signal OUT outputted from the OR 20 remains held in an xe2x80x9cLxe2x80x9d state.
Similarly, even if the clock signal CLK inputted to the input terminal 11 changes to the level xe2x80x9cHxe2x80x9d at a time T3 while the detection signal OUT of the OR 20 is xe2x80x9cLxe2x80x9d, and the clock signal CLK inputted to the input terminal 11 changes to the level xe2x80x9cLxe2x80x9d at a time T4 while the detection signal OUT of the OR 20 is xe2x80x9cLxe2x80x9d, the detection signal OUT outputted from the OR 20 is always held in the xe2x80x9cLxe2x80x9d state.
Now consider where the oscillator circuit stops operating at a time T5, for example, and the clock signal CLK supplied to the input terminal 11 remains held in an xe2x80x9cHxe2x80x9d state. Since the NMOS 12 is brought to an on state and the PMOS 13 is brought to an off state, the node N11 is reduced to the level xe2x80x9cLxe2x80x9d. On the other hand, the NMOS 16 is brought to an off state and the PMOS 17 is brought to an on state, whereby the potential at the node N12 rises. The potential at the node N12 rises gently, and a detection signal OUT outputted from the OR 20 goes xe2x80x9cLxe2x80x9d for a while. However, if this state goes on, then the potential at the node N12 reaches the threshold voltage Vt of the OR 20 and the detection signal OUT outputted from the OR 20 goes xe2x80x9cHxe2x80x9d at a time T6.
Contrary to the above, when the oscillator circuit is deactivated in a state in which the clock signal CLK supplied to the input terminal 11 is xe2x80x9cLxe2x80x9d, the NMOS 16 is turned on and the PMOS 17 is turned off, so that the node N12 is reduced to the level xe2x80x9cLxe2x80x9d. On the other hand, when the NMOS 12 is brought to an off state and the PMOS 13 is brought to an on state, and hence the potential at the node N11 rises. The potential at the node N11 rises gently, and a detection signal OUT outputted from the OR 20 goes xe2x80x9cLxe2x80x9d for a while. However, if this state goes on, then the potential at the node N11 reaches the threshold voltage Vt of the OR 20 and the detection signal OUT outputted from the OR 20 goes xe2x80x9cHxe2x80x9d.
Thus, the conventional oscillation stop detection circuit is provided with two sets of circuits for detection in association with the level xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d at the time that the clock signal CLK stops. Further, the values of the resistor 14 and capacitors 18 and 19 are suitably set according to the cycle of a clock signal CLK to be detected. While the stable clock signal CLK is being inputted, the detection signal OUT is rendered xe2x80x9cLxe2x80x9d and outputted in its state. When the clock signal CLK stops, the detection signal OUT is rendered xe2x80x9cHxe2x80x9d and outputted in its state.
However, the conventional oscillation stop detection circuit has the following problems.
Namely, the two sets of circuits for detection are provided in association with the case where the clock signal CLK stops in the xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d state, and their configurations are complex. In particular, a problem arises in that in order to assure the stable detecting operation, the values of the resistor 14 and capacitors 18 and 19 must be designed larger, whereby the oscillation stop detection circuit increases in pattern area and the IC increases in chip size.
An object of the present invention is to provide an oscillation stop detection circuit capable of solving a problem involved in the prior art, reducing a pattern area and reliably detecting the stop of oscillation.
In order to solve the problem, an oscillation stop detection circuit comprises delay means for delaying an oscillation signal having a predetermined cycle by a predetermined time to thereby output a delayed signal therefrom, detecting means for exclusive-ORing the oscillation signal and the delayed signal to thereby detect the presence of the oscillation signal and outputting a pulse signal in the predetermined cycle when the oscillation signal exists, and charge and discharge means having a capacitor electrically connected between an output node for outputting a detection signal indicative of whether the oscillation signal is at a stop and a source potential or a ground potential, and for discharging the capacitor when the pulse signal is supplied and charging the capacitor according to a predetermined time constant while the pulse signal is unsupplied.